1. Field of the Invention
This invention relates generally to transconductance circuits, and more particularly to a technique to control the transconductance of a resistor degenerated transconductance circuit to within a few percent without a tuning loop.
2. Description of the Prior Art
Conventional transconductance circuits have a transconductance value that varies with semiconductor processing. Such circuits often use resistors to achieve high linearization, but typically suffer from a transconductance value that varies as much as +/xe2x88x9225% or even more. These transconductance circuits require extra circuitry in the form of tuning loops to bring the transconductance value with an acceptable range.
Other known solutions for tunable transconductance use CMOS devices operating in the triode region to either degenerate a differential pair or to proportion a variable amount of current generated from a linearized input pair to an output stage. The triode device generally tends to decrease the dc gain of the transconductor and also requires some form of a closed tuning loop to adjust the transconductance to a specific value.
In view of the foregoing, a need exists for a process-insensitive, highly-linear, constant transconductance circuit that does not require extra circuitry in the form of tuning loops to bring the transconductance value with an acceptable range.
To meet the above and other objectives, the present invention employs a technique to control the transconductance of a resistor degenerated transconductance circuit to within a few percent without a tuning loop. Specifically, a CMOS multiplier is used in the signal path, that is offset biased with a specific combination of currents and which compensates for transconductance variations due to resistor processing variations.
Illustrated in FIG. 1 is a highly-linear, process-insensitive, constant transconductance circuit 100 according to one embodiment of the present invention. The input stage consisting of amplifiers A1 and A2, CMOS transistors M11, M12 and resistor R is well-known in the prior art and yields a transconductance that is highly linear and inversely proportional to resistor processing. An offset biased CMOS multiplier a consisting of devices M3-M6 is used as the cascode portion of a folded cascode stage. The offset is generated by forcing current I1 to be greater than current I2. The overall circuit transconductance is kept constant by implementing currents I1 and I2 such that they are specific combinations of reference currents, one generated by a bandgap voltage and an external resistor and the other generated by a bandgap voltage and an internal resistor, such as illustrated in FIG. 8. The compensating/bias currents are also used to bias the remaining portions of the transconductance circuit. The overall bias current increases with lower resistor processing with the above discussed current I1 and I2 combinations. This aids in preventing the input stage from limiting and causing distortion when the resistor processing is low, and also ensures that less current is dissipated for the same distortion level when the resistor processing is high. The CMOS multiplier is implemented using low threshold voltage devices, allowing additional cascode of low threshold voltage devices to be placed between the CMOS multiplier and the outputs, which has the added advantage of keeping the drain voltages of CMOS devices M3-M6 equal.
In one aspect of the invention, a constant transconductance circuit is implemented with a specifically biased CMOS multiplier to proportion a variable amount of current generated from a linearized input pair to an output stage in which all devices are sustained in the saturation region to keep the dc gain high.
In another aspect of the invention, a constant transconductance circuit is implemented with a CMOS multiplier properly biased to keep the overall transconductance insensitive to resistor process variations and therefore to negate the need for a transconductance tuning loop.
In yet another aspect of the invention, a constant transconductance circuit is implemented with a CMOS multiplier that acts as a cascode to provide high output impedance and hence high dc gain.
In still another aspect of the invention, a constant transconductance circuit is implemented with a CMOS multiplier in which the currents that bias the multiplier can be used to bias the entire transconductance stage, wherein the currents are partially proportional to the internal resistor such that the input stage bias compensates for resistor variation using the least amount of power to keep the total harmonic distortion (THD) constant for a maximum input signal.
In still another aspect of the invention, a constant transconductance circuit is implemented having a highly-linear input stage and provides a process and temperature insensitive, constant transconductance without the need for a closed tuning loop.
In still another aspect of the invention, a constant transconductance circuit is implemented with a CMOS multiplier to proportion the transconductance to the output stage rather than a triode device such that the dc gain is not degraded.
In still another aspect of the invention, a constant transconductance circuit is implemented with a CMOS multiplier in which the sources of the devices in the multiplier provide a low-impedance point that can be connected to multiple input stages sharing a common output stage to reduce power consumption.
As used herein, resistor processing is the variation in resistance that occurs when an integrated circuit (IC) if processed in a wafer fabrication facility in which the resistors in the IC do not have consistent values from either chip to chip or wafer lot to wafer lot. The values of these components will vary due to semiconductor manufacturing process variations. In many semiconductor processes, for example, the polysilicon resistor sheet resistance can vary +/xe2x88x9225%. A 10 kOhm resistor on a chip, therefore, can vary from 7.5 kOhms to 12.5 kOhms due to variations in resistor processing. Resistor processing then, is basically how the resistor values will vary due to slight variations in the manufacturing process. An input stage having a transconductance that is inversely proportional to resistor processing, therefore, means that if the resistors on a chip happen to be processed 25% high (12.5 kOhms using the example above), then the transconductance of that stage will be (1/1.25) or 0.8X low (or xe2x88x9220%).